Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques
碩士 === 國立中央大學 === 電機工程研究所 === 93 === When the efficiency of the speed with the very large-scale integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, e...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78895657415766774608 |