A PLL Based COMS Frequency Synthesizer for Low-Power WCDMA Applications
碩士 === 國立彰化師範大學 === 電機工程學系 === 93 === This thesis presents a 1.8 V 2GHz band low-power CMOS frequency synthesizer designed in TSMC 0.18µm 1P6M RF/Mixed-Signal CMOS process that meets the WCDMA specifications. In that, we propose a fast simulation model for the design of PLL. We employ a stable compl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21618956079345879279 |