Design of a CMOS Delay-Locked Loop Based Programmable Frequency Multiplier
碩士 === 國立東華大學 === 電機工程學系 === 93 === In this thesis, a CMOS delay-locked loop based frequency multiplier is presented. The proposed phase selector is used for programmable function. The proposed frequency multiplier circuit can multiply the frequency of input signal without a jitter accumulation prob...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/95223110010082388862 |