| Summary: | 博士 === 國立清華大學 === 動力機械工程學系 === 93 === During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications such as flip-chip, wafer-level packaging, fine-pitch ball grid array (BGA), and chip-scale packaging (CSP). The solder joint shape-prediction methods have been incorporated as a design tool to enhance the reliability of the wafer-level packaging. As the demand for portable electronic equipment increases, wafer-level chip-scale-packaging (WLCSP) is expected to be widely used in static-dynamic random access memory (SDRAM) for its better electrical performance and lower manufacturing costs. However, reliability of solder joints for a large chip size such as 6mm ´ 6mm without underfill assembly is still in question. In conventional WLCSP, the dimensions of each solder ball and each solder pad are the same. The maximum thermally induced stress/strain contours occur on the die-side surface of the solder joint furthest away from the chip center. In this research, a hybrid method combining an analytical algorithm and the energy-based approach are applied to predict standoff heights and geometry profiles of the solder joints. A hybrid-pad-shape (HPS) system is also proposed to design solder ball layout and to enhance the reliability of solder joints. The HPS system contains at least two kinds of solder volume and pad size/shape as well as their relative locations during the reflow process. Next, the commercial finite-element code ANSYSâ is used to simulate the stress/strain behavior of the solder balls in WLCSP under cyclic temperature loadings. A nonlinear and parametric finite-element analysis is conducted to investigate the reliability issues that result from several design parameters. In this research, several experimental validations are completed to verify the correctness and feasibility of solder-joint shape-prediction methods and finite-element analysis procedures. The design parameters considered in this research include solder-joint layout, solder volume, pad diameter, die thickness, and thickness/material properties of the stress buffer layer (SBL). In the aspect of solder joint layout design, the solder joints located in the corner areas can be considered as structure dummy balls with no electrical signals pass through them. This research also discusses the effects of manufacturing errors of design parameters on the reliability of solder joints. The results reveal that as the WLCSP contains larger round pad or suitably oriented elliptical-pad solder joints located in the corner areas underneath the chip, the maximum equivalent plastic strain of the solder joints will be effectively reduced and the solder-joint fatigue life under thermal loading will be greatly enhanced. In addition, thinner die and thicker SBL that have lower Young’s modulus and higher CTE are also good for better reliability in the WLCSP. On the other hand, minor manufacturing errors of design parameters result in unfavorable effects on solder-joint reliability. Therefore, designers should seek the optimal design of electronic components using systematic parametric analysis and accurate control of manufacturing processes so as to ensure superior quality. Furthermore, the findings presented in this research can be used as a design guideline for electronic packaging with area-array interconnections such as CSP, flip-chip packaging, Super CSP and fine-pitch BGA.
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