On-Chip Jitter Measurement Circuits for Phase-Locked Loops
碩士 === 國立清華大學 === 電機工程學系 === 93 === In this thesis, we present an on-chip circuit to measure the worst-case period jitter induced by noise for phase-locked loops (PLLs). The circuit uses a digitally controlled delay line to track the extreme period width of the measured signal, thus the worst timing...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44128958969979241426 |