Feasibility Study of HOY─A Wireless Test Methodology for VLSI Chips and Wafers
碩士 === 國立清華大學 === 電機工程學系 === 93 === As we enter the deep submicron age, the continuous improvement of manufacturing technologies has made SoC possible. However, it also brings a lot of challenges in testing. Higher pin count will make it more difficult to probe the dies on the wafer. At speed test i...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/67103063763164758352 |