Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock
碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In this thesis, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18um bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purpo...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59909025329939451082 |