SOC Test Scheduling Using Sequence-Pair Representation
碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === With the growing complexity of SOC designs, the SOC test scheduling problem becomes a great issue. A good test scheduling can greatly decrease the total test time. When we investigate the scheduling problem, the power consumption, TAM bus assignment, and individ...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40601000452736936349 |