An FPGA design and implementation of the AES in OCB mode of operation
碩士 === 大同大學 === 電機工程學系(所) === 93 === In this thesis, we use FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply) to design AES_OCB mode operation. We use Verilog, Xilinx ISE 6.1 and ModelSim to design simulate and implement. The number of CLB slices is 3552.The operating clock rate is 61.31MHz. D...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4nrazr |