Design of All-Digital Delay Locked Loop in Nano-CMOS Technology
碩士 === 國立中正大學 === 電機工程所 === 94 === There are two structures (iHDSC & ABSDLL) for different applications in this thesis . All of the two structures are using the delay difference conception which can achieve low power, low jitter, high resolution and high P.V.T. variation resistance. With the con...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23270819307134813677 |