An FPGA design of a performance-improved 8-bit RISC microprocessor
碩士 === 長庚大學 === 電子工程研究所 === 94 === In this thesis, we use Verilog Hardware Description Language (HDL) to design an 8-bit RISC microprocessor. Here, we first efficiently reorganize the input clock scheme. In addition, using the pipelining structure the instruction cycle is further reduced to two inpu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62904091655421985678 |