| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 94 === With the progressing of Semiconductor Fabrication Techniques, more and more transistors have been accommodated in a single chip. Upon the challenges of complexity and difficulty, the System-On Chip and embedded system have gradually merged into the main stream of chip design. Since the addition of fault tolerant system into the chip design would boost the factors in a single system as well as the complexity of design, we propose a technique which can promote the fault tolerant system to a behavioral level or even the higher abstract level. Moreover, a short-time simulation and verification procedures will be constructed. Due to the restriction of VHDL, SystemC has been chosen as an better developing environment to promote the design level into a higher abstract level.
The topic of this thesis is to test the capability of error tolerant of Very Long Instruction Word (VLIW) processors in two different I.C. design environments, which are based on SystemC and VHDL platforms. In addition, due to the different inject logics in VHDL and SystemC, the variation of the applications under two different environments will be discussed. Because faults and errors are injected for VHDL and SystemC platform, respectively, such differences will also be discussed in this thesis. Moreover, the ratio of Fault-caused-Error and the error existed period occurred upon various environments will be tested based on SystemC platform. Also, we will discuss the influences to experimental errors caused upon the two different platforms, as well as provide our valuable experimental experiences. Such experiences will provide more accurate experimental results in terms of error simulation once the fault tolerant design and design environment are promoted to a higher level.
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