A design of analog-to-digital converter for IEEE 802.11a WLAN system
碩士 === 中華大學 === 電機工程學系(所) === 94 === This work describes an analog-to-digital converter which has 10 bit resolutions and 40MHz sampling rate. This analog-to-digital (ADC) converter is used nine-stage pipelined and fully differential structure. Because of the digital error correction is adopted in th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15120230183704361800 |