A Fast Lock and Adjustable Dual-Slope PLL with an Automatic Current Controler
碩士 === 中華大學 === 電機工程學系碩士班 === 94 === In the design of phase-locked loops (PLLs), we must take a tradeoff between low jitter and settling time. Most phase-locked loops are required to have low phase noise or low jitter under the condition of fast locking for wireless communications system. Therefore,...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77521685175656551938 |