A Fast Lock and Adjustable Dual-Slope PLL with an Automatic Current Controler
碩士 === 中華大學 === 電機工程學系碩士班 === 94 === In the design of phase-locked loops (PLLs), we must take a tradeoff between low jitter and settling time. Most phase-locked loops are required to have low phase noise or low jitter under the condition of fast locking for wireless communications system. Therefore,...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77521685175656551938 |
| Summary: | 碩士 === 中華大學 === 電機工程學系碩士班 === 94 === In the design of phase-locked loops (PLLs), we must take a tradeoff between low jitter and settling time. Most phase-locked loops are required to have low phase noise or low jitter under the condition of fast locking for wireless communications system. Therefore, an automatic current controller technique is proposed to increase the settling speed and reduce the ripple of control voltage. This paper presents an adjustable dual-slope PLL with an automatic current controller to adjust the currents of the charge pump by adjusting loop bandwidth from phase error between input reference signal and feedback signal.
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