A High-speed Charge Pump with Two Charge Currents for PLL
碩士 === 中華大學 === 電機工程學系碩士班 === 94 === In this thesis, we design a high speed phase-locked loop (PLL).The circuit is simulated and verified by Hspice with TSMC 0.18μm technology.A PLL consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01487085345502572809 |