Voltage Scaling and Voltage Island Construction at Floorplan Stage for Low Power IC Design
碩士 === 中原大學 === 資訊工程研究所 === 94 === As the CMOS technology progressed, more devices can be packed in a single chip. And power consumption becomes a key challenge in chip design. In this paper, we propose a voltage scaling, floorplaning and voltage island construction algorithm to reduce power consump...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59238268306029759604 |