Voltage Scaling and Voltage Island Construction at Floorplan Stage for Low Power IC Design

• Main Authors: Sung-Han Tsai, 蔡松翰
• Other Authors: Mely Chen Chi
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/59238268306029759604

碩士 === 中原大學 === 資訊工程研究所 === 94 === As the CMOS technology progressed, more devices can be packed in a single chip. And power consumption becomes a key challenge in chip design. In this paper, we propose a voltage scaling, floorplaning and voltage island construction algorithm to reduce power consumption by assigning the supply voltage of standard cells of non-critical paths to the low supply voltage and construct voltage islands. Our algorithm includes the following steps: (1) Calculate the cycle time. (2) Assign all standard cells to the low voltage. (3) Cluster standard cell according to the connectivity and the slack. (4) Floorplan to minimize the number of cells with negative slack and the dead space. (5) Correct timing violation by assigning the supply voltage of standard cells to high. (6) Voltage scaling refinement under timing constraint to reduce power consumption. (7) Voltage island planning. (8) Floorplan refinement to minimize the number of cells with negative slack and the dead space. Differ from the previous works, we cluster standard cells according to the connectivity and the slack then floorplan the clusters. We assign the supply voltage of standard cells after the floorplanning and the timing information is more accurate. After voltage scaling, we perform voltage island planning. Our algorithm can assign the supply voltage and plan the voltage islands automatically. We apply the algorithm to five test cases. Experimental results show that the proposed algorithm reduces the power consumption by 53% on the average.