The Implementation and Analysis of an All-digital Phase-Locked Loop
碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 94 === Abstract An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/y84b7d |