The Implementation and Analysis of an All-digital Phase-Locked Loop

• Main Authors: Hung-Lung Su, 蘇鴻隆
• Other Authors: Po-Yueh Chen
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/y84b7d

碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 94 === Abstract An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO. This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.