The Implementation and Analysis of an All-digital Phase-Locked Loop
碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 94 === Abstract An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in...
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ndltd-TW-094CYUT53920212019-05-15T19:17:50Z http://ndltd.ncl.edu.tw/handle/y84b7d The Implementation and Analysis of an All-digital Phase-Locked Loop 實現與分析一個全數位鎖相迴路 Hung-Lung Su 蘇鴻隆 碩士 朝陽科技大學 資訊工程系碩士班 94 Abstract An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO. This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications. Po-Yueh Chen 陳伯岳 2006 學位論文 ; thesis 42 en_US |
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碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 94 === Abstract
An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time.
A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO.
This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.
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author2 |
Po-Yueh Chen |
author_facet |
Po-Yueh Chen Hung-Lung Su 蘇鴻隆 |
author |
Hung-Lung Su 蘇鴻隆 |
spellingShingle |
Hung-Lung Su 蘇鴻隆 The Implementation and Analysis of an All-digital Phase-Locked Loop |
author_sort |
Hung-Lung Su |
title |
The Implementation and Analysis of an All-digital Phase-Locked Loop |
title_short |
The Implementation and Analysis of an All-digital Phase-Locked Loop |
title_full |
The Implementation and Analysis of an All-digital Phase-Locked Loop |
title_fullStr |
The Implementation and Analysis of an All-digital Phase-Locked Loop |
title_full_unstemmed |
The Implementation and Analysis of an All-digital Phase-Locked Loop |
title_sort |
implementation and analysis of an all-digital phase-locked loop |
publishDate |
2006 |
url |
http://ndltd.ncl.edu.tw/handle/y84b7d |
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