Designing of Image Compression Memory Hierarchy for Embedded System
碩士 === 大葉大學 === 資訊工程學系碩士班 === 94 === Designing of modern computers’ micro-architecture relies on dynamic instruction traces for design optimization. However, dynamic instruction traces often generates massive data that make the traces difficult to analysis and process. This thesis propose a novel dy...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25638517714195136498 |
| Summary: | 碩士 === 大葉大學 === 資訊工程學系碩士班 === 94 === Designing of modern computers’ micro-architecture relies on dynamic instruction traces for design optimization. However, dynamic instruction traces often generates massive data that make the traces difficult to analysis and process. This thesis propose a novel dynamic instruction traces profiling framework and a profiling algorithm that named as Melting in mining of the most frequent and longest instruction sequence. The profiling framework is exemplified by designing of memory hierarchy for JPEG image compression algorithm.
The proposed profiling framework combines both the merits of traditional functional profiling and modern instruction traces schemes. The framework is divided into to two steps. The target program is first profiled using function level profiler that the most frequent function is determined. The derived function is simulated using the SimpleScalar/ARM 4.0 simulator where dynamic instruction traces is generated. As result, the amount of traces data is greatly reduced. Finally, having the traces obtained, the Melting Algorithm is applied to mine the most frequent and longest consecutive instruction sequence. The mined sequence is applied to optimized memory hierarch. The sequence can also be applied in instruction compression and other micro-architecture design issues.
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