Design a Bilt-In Circuit Delay Self Testing Methodology
碩士 === 逢甲大學 === 產業研發碩士班 === 94 === The accurate delay measurement is a major issue to test advanced SoC chips. Today, the question was use the ATE for testing. But low/noisy supply voltage design will induces CUT delay, and makes the ATE or scan testing technique hard to capture the correct output d...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
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2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19164658140160032434 |