Design a Bilt-In Circuit Delay Self Testing Methodology

• Main Authors: Chiu-Mao Yang, 楊秋茂
• Other Authors: Ching-Hwa Cheng
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/19164658140160032434

碩士 === 逢甲大學 === 產業研發碩士班 === 94 === The accurate delay measurement is a major issue to test advanced SoC chips. Today, the question was use the ATE for testing. But low/noisy supply voltage design will induces CUT delay, and makes the ATE or scan testing technique hard to capture the correct output delay responses. So we propose a built-in circuit delay self testing (DBIST) methodology. Use the Built-in delay testing circuit to detect the Circuit Under Test(CUT) of delay time and scan-out of the result. In the circuit of delay, We use the Veriner Delay Line(VDL) measure circuit to modify, and propose a new structure of VDL measure circuit to decrease the area and power consumption. It’s also can decrease the time of data scan out . So, we have emphasize the VDL of measure analysis, stable, area and power consumption adjust and simple the circuit of structure . When the measure analysis and stable have to improve, that it can be measure the circuit of delay time and error . Keyword：BIST(Built-In Self Testing)、VDL(Vernier Delay Line)