All Digital Phase Lock Loop Using Signal-Edge-Trigger DCO
碩士 === 輔仁大學 === 電子工程學系 === 94 === An all-digital phase locked-loop (ADPLL) is presented to achieve fast lock, high resolution and process immunity. A novel digitally controlled varactor (DCV) is used in fine-tuning delay cell design. The proposed DCO architecture uses Single-Edge-Trigger DCO. Thus,...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/25730471276305357522 |