A Design of BIST on the IEEE P1500 Complied CPU Core
碩士 === 義守大學 === 電子工程學系碩士班 === 94 === This project presents a design of Built-In Self-Test (BIST) on the IEEE P1500 complied CPU core. In RISC CPU, The functions we improved such as new instructions, new addressing mode, pipeline, branch prediction and relative address. In the BIST design, PRPGs and...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34451766115632090374 |