Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
碩士 === 國立中興大學 === 資訊科學系所 === 94 === In this paper, we propose a layout-aware scan tree synthesis methodology. Scan tree can greatly reduce test data volume, which is very desirable in SOC testing. However, previous researches on scan tree synthesis have not considered routing issues in physical desi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25873079791099251500 |