A Bandwidth Guaranteed and Low Latency Lottery-basedArbiter Design for On-Chip Bus Communication
碩士 === 中興大學 === 電機工程學系所 === 94 === Since the integrated circuits make electrical technologies develop increasingly, the logic electric circuits are gradually complicated, and the system electric circuits gradually become huge, and then the number of master and slaver units already can''t s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28017874099170327765 |