Design and Implementation of Low Noise Amplifier for 3 to 6 GHz UWB Application
碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 94 === The thesis uses TSMC 0.18 1P6M CMOS process to design and implement the “ four to six GHz LNA ”, “ three to six GHz LNA ”, and “ three to seven GHz LNA. ” The simulate results for Noise Figure（NF）of the three chips are all lower than 5 dB, and S11 or S22 ar...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/10564918503258894547 |