Modeling of Thin Film Induced Substrate Stress and Its Application in Semiconductor Device Isolation Process

• Main Authors: Ping-Shine Chang, 張平昇
• Other Authors: Kuo-Shen Chen
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/02918180569470553378

碩士 === 國立成功大學 === 機械工程學系碩博士班 === 94 === Isolation techniques are essential for semiconductor device for reducing interferences between devices for sub-micro and sub 100-nm fabrication process. By separating active regions with oxide isolation structures, it is possible to reduce cross-talk between elements. However, the mismatch in thermal mechanical properties between oxide and silicon create enormous stress and it results leakage current due to generation of dislocations in active zones. As a result, it is important to carefully design the isolation structures. However, at this moment, all designs are based on finite element analysis, its trial and errors and case by case nature cause difficulty for systematic understanding and design for this problem. A semi-analytical procedure is demand. In this thesis, the stress behavior of STI structure is firstly modeled and is properly reduced to a simple model. By utilizing the Cerruti’s Problem or Hu’s Formula as the kernel function. The stress distribution of STI isolation structure can be found by using Green’s function approach. By this approach, the designer can perform a rapid conceptual design and then use more detail finite element analysis for design optimization only. The overall computational cost or working time can be effectively reduced. The proposed method is then validated by finite element simulation by using a simple plane strain structure and three-dimensional model of simple surface pattern as the test and verify model. By this approach, a computer program, called I-SA, is constructed to evaluate the stress subjected to arbitrary isolation structures. The program could provide preliminary stress analysis information for conceptual design of isolation structures. The designer could improve the designs according the results of the stress analysis. And the results show that the proposed method can essentially catch the stress distribution. Using the same conception, the proposed method can also be applied to other semiconductor structure, such as multi-layer interconnection structures.