Applying Ford 8D and Theory of Constraints Problem Solving Discipline for OEE Improvement of CMP Process
碩士 === 國立交通大學 === 工學院碩士在職專班精密與自動化工程學程 === 94 === In new generation of semiconductor memory and logical device developing process, in order to reduce the cost, the tendency is to increase aspect ratio and add more metal layers. The Chemical Mechanical Polishing is applied to planarization process of...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69272318567039159421 |