Low Power All Digital Phase-Locked Loop with Built-In Jitter Self Test
碩士 === 國立交通大學 === 電子工程系所 === 94 === A new architecture and algorithm for the all digital phase-locked loop (ADPLL) with low power design is presented in this thesis. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, w...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/uhgc5q |