The Design and Analysis of a CMOS 8bit 50MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立交通大學 === 電子工程系所 === 94 === The thesis describes the design of a 3.3 V, 8-bit, 50M sample/s CMOS pipelined analog-to-digital converter (ADC) implemented by simulation with 0.35um double-poly four-metal process. The component in the ADC is the residue amplifier, the dynamic comparator, the fl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4zw5xs |