BIST Burn-in Methodology for the CMOS Circuit
碩士 === 國立交通大學 === 電子工程系所 === 94 === This thesis proposes and studies a BIST burn-in methodology which is aimed to finding early failure in CMOS SOC testing. It is to, on-chip, apply a set of patterns which maximizes the power dissipation to burn-in test the CUT without resorting to the conventional...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/z7qbsb |