Performance of SRAM with Nanoscale Transistors

• Main Authors: Chien-Sung Lu, 呂建松
• Other Authors: Tiao-Yuan Huang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/95674822677830684325

碩士 === 國立交通大學 === 電子工程系所 === 94 === Silicon-based planar MOSFETs have been the building block for SRAM. However, as the design rule continuously shrank down beyond the 45 nm, conventional planar CMOS devices encounter significant challenges. Many three-dimensional (3D) structure transistors, such as the bulk fin field-effect transistor (Bulk FinFET), SOI fin field-effect transistor (SOI FinFET), multiple-gate FinFET, and surrounding-gate nanowire FinFET (Nanowire FinFET) have been proposed, fabricated, and demonstrated more attractive electrical characteristics than that of single-gate planar devices. Two aspects are important for SRAM cell design: the cell area and the stability of the cell. The cell area determines about two-third of the total chip area. The cell stability determines the soft-error rate and the sensitivity of the memory to process tolerance and operating conditions. The two aspects are interdependent since designing a cell for improved stability invariably requires a larger cell area. In this thesis, we study the performance of 6-T SRAM cell with three different building 32 nm devices, planar MOSFETs, SOI FinFETs, and nanowire FinFETs. The stability and sensitivity analysis will be discussed. Static noise margin (SNM) of SRAM is computational investigated and compared by using a mixed-model three-dimensional device simulation with considering quantum mechanical effects. We firstly analyze and compare the intrinsic and terminal characteristics for the three different transistors in SRAM cells. Also, the SNM of SRAM during both hold and read modes is explored for the device with respect to different supply voltage , cell ratio, and operation temperature. With the scaling of conventional CMOS devices to sub-100 nm and beyond, the variations of the transistor characteristics due to local and non-local effects, such as the random dopants, the critical dimension of channel length, the interface roughness, and line edge roughness (LER) start to adversely affect the yield and functionality of the corresponding circuits. In this thesis, a systematical method for sensitivity analysis of SRAM cells with different device structures is developed. Based on a design of experiment (DOE), a mixed-mode (i.e., coupled device and circuit) simulation, and a response surface model (RSM), performances of 6T SRAM cells are explored with respect to static noise margin (SNM). Taking the channel length of different transistors in a 6-T SRAM cell as significant variables, a SNM response surface model is constructed. With the developed SNM model, the impact of channel length variation on SNM is evaluated. Finally, the purpose of this study is to provide a systematically statistical method to analysis the performance of the SRAM cell using nano-scale device structures. The stability of SRAM cells is explored by a 3D mixed-mode simulation. The sensitivity analysis of SNM will be studied by the combination of design of experiment and second-order response surface model. We believe that he design of 6-T SRAM cell with nanowire FinFETs is a promising approach in sub-45 nm CMOS devices era.