Design to Enhance Turn-on Uniformity of Multi-Finger ESD Protection Devices

碩士 === 國立交通大學 === 電子工程系所 === 94 === To sustain the required ESD levels, the device size of NMOS used in ESD protection circuit is often designed with large device dimensions, which are often drawn with the multi-finger layout style to reduce the total occupied silicon area. However, because of the o...

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Bibliographic Details
Main Authors: Jia-Huei Chen, 陳佳惠
Other Authors: Ming-Dou Ker
Format: Others
Language:en_US
Published: 2006
Online Access:http://ndltd.ncl.edu.tw/handle/06121128597368466573
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Summary:碩士 === 國立交通大學 === 電子工程系所 === 94 === To sustain the required ESD levels, the device size of NMOS used in ESD protection circuit is often designed with large device dimensions, which are often drawn with the multi-finger layout style to reduce the total occupied silicon area. However, because of the obvious snapback breakdown characteristic of NMOS transistor and the layout geometry effect on the distributed base resistance of each parasitic lateral bipolar transistor, multi-finger NMOS cannot be triggered on uniformly under ESD stress. The ESD current is only concentrated on some fingers. Therefore, the ESD robustness of multi-finger NMOS cannot be increased linearly with the increase of device size. The aim of this thesis is to improve the turn-on uniformity of multi-finger NMOS. Objective of the proposed designs are to solve the non-uniform turn-on issue through simple circuit wiring of the multi-finger NMOS itself, and without external triggering circuit and increase of layout area. The first proposal is self-substrate-triggered technique applied to gate-grounded NMOS (GGNMOS). The design concept is to utilize the current of the most easily turned-on center fingers to trigger the substrate of all the other fingers. This design has been successfully verified in a 0.13-um CMOS process, and the ESD robustness of self-substrate-triggered GGNMOS could be improve twice larger than that of traditional GGNMOS. The second proposal is equal-substrate-potential technique applied to stacked-NMOS devices, and the design is verified in a 0.18-um CMOS process. The design concept is to equalize the substrate-potential of each parasitic lateral BJT inherent in stacked-NMOS and thus improve the turn-on uniformity. The experimental results show that equal-substrate-potential stacked-NMOS has smaller turn-on resistance than traditional stacked NMOS. The HBM ESD level could be improved through this design, but the MM ESD level is the same as traditional stacked-NMOS. Contents of this thesis have already been published on an international conference, a local conference, and accepted by an international journal.