A LOW POWER ADPLL-BASED FREQUENCY SYNTHESIZER FOR HIGH SPEED CLOCK GENERATION
碩士 === 國立交通大學 === 電子工程系所 === 94 === This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design. By using the new type digitally controlled delay element (DCDE), a digitally c...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99909741280710529747 |