An Ultra-Wideband CMOS Power Amplifier for 3.1 to 10.6 GHz Wireless Applications
碩士 === 國立交通大學 === 電子工程系所 === 94 === This thesis is based on TSMC 0.18um CMOS process. A two-stage ultra-wideband CMOS power amplifier is applied for 3.1 to 10.6GHz. The 1st stage introduces the common-source and common-gate topology called “cascade” with the resistor feedback configuration. It bring...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06126230117781025070 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 94 === This thesis is based on TSMC 0.18um CMOS process. A two-stage ultra-wideband CMOS power amplifier is applied for 3.1 to 10.6GHz. The 1st stage introduces the common-source and common-gate topology called “cascade” with the resistor feedback configuration. It brings higher power gain and wideband input impedance match. And the 2nd stage utilizes the common-source with resistor and inductor in order to wideband matching and power gain flatness.
After further studying for the above-mentioned power amplifier, we improve the detail and design a two-stage power amplifier for 3 to 8GHz. By adding a capacitor to the feedback path, both feedback configurations at the 1st and 2nd stages decreases the DC power loss. And we obtain more suitable DC bias condition by focusing on the load-line design; it does work very much to our efficiency and linearity.
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