Low k Barrier All-in-one Etch Study of Copper Dual Damascene Process
碩士 === 國立交通大學 === 工學院碩士在職專班半導體材料與製程設備學 === 94 === In the era of deep submicron semiconductor fabrication, interconnection resistance-capacitance (RC) time delay dominates the performance of whole integrated circuits (ICs). To mitigate the issue, two realistic methods are accepted popularly. The firs...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93570281843115800404 |