All Digital CMOS Self-sample Vernier Delay Line Circuit for Clock Jitter Measurement
碩士 === 國立中央大學 === 電機工程研究所 === 94 === As the improvement of semiconductor technology, VLSI circuits has developed into System-On-a-Chip（SoC）. When many systems integrated into a chip, the sequence of clock of every circuit must be accurate. In the system, clock skew will affect the performance of the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/xwm5ks |