All-Digital Arbitrary Duty-Cycle Synchronous Mirror Delay Circuits
碩士 === 國立中央大學 === 電機工程研究所 === 94 === In view of the current SOC systems, a great deal of circuits is integrated on a chip and the clock signal is entirely distributed. The clock synchronization, therefore, becomes truly an important issue on it. Phase-locked loop (PLLs) and delay-locked loop (DLLs)...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/qp95uh |