On Analog Behavioral Modeling for ΣΔDAC with Non-Ideal Effect
碩士 === 國立中央大學 === 電機工程研究所 === 94 === With the process technology innovating rapidly, the device size is continuing to scale down. In SoC era, traditional design techniques must be modified to solve the integration problems with over million gate counts in a single chip. The major design challenge is...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82afyj |