An ILP-Based Scheme for Low Power Scheduling in a VLIW Architecture Operating at Multiple Voltages
碩士 === 國立東華大學 === 資訊工程學系 === 94 === In this thesis, we propose a new framework for minimizing the total power consumption and the peak power in a very long instruction word (VLIW) architecture. Both the total power consumption and the peak power are critical issues in low power design. The total pow...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01408244260621815204 |