| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 94 === This thesis proposes a built-in current sensor (BICS) circuit design for IDDQ testing in SRAM applications. IDDQ testing is a powerful technique for detecting defects in CMOS circuits. The general idea of the IDDQ testing is to measure and observe the short current of the circuit at the steady state. Generally, the BICS is one of the most important circuits to implement the IDDQ testing approach for on-chip testing. A novel BICS design with high speed and low voltage drop is presented in this thesis. The character of the small voltage drop can not only effectively reduce the influence of the BICS accuracy but also avoid the impact of the circuit under test (CUT). Reliability analysis shows that the proposed BICS can be correctly working for temperature, process and supply voltage variations. A static random access memory (SRAM) is used as the CUT herein to discuss the testing considerations, including fault models and IDDQ testing scheme. Also, the physical chip design by using TSMC 0.18-um CMOS technology is presented to verify the feasibility of an IDDQ testing scheme based on the proposed BICS. Simulated results and physical layouts indicate that the IDDQ testing scheme based on the proposed BICS possesses high fault coverage (100 %) and low area overhead (2.5 %). Briefly, this thesis proposes a low-cost BICS design for IDDQ testing in SRAM applications.
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