Fast Buffered Delay Estimation Considering Process Variations
碩士 === 國立清華大學 === 資訊工程學系 === 94 === Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations becomes critical to ensure high parametric timing yield. During the design stage, fas...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35840191708629162710 |