A Timing-Aware Force-Directed Algorithm for Wirelength-Driven Standard Cell Placement using Path Grouping
碩士 === 國立清華大學 === 資訊工程學系 === 94 === Placement always plays an important part in a back-end design flow and is an active research area for many years, because it significantly affects the routability, chip size, chip power, and chip performance. In this thesis, we propose a timing-aware standard-cell...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49679730094131006362 |