A Timing-Aware Force-Directed Algorithm for Wirelength-Driven Standard Cell Placement using Path Grouping

• Main Authors: Bo-Wei Chen, 陳柏偉
• Other Authors: Ting-Chi Wang
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/49679730094131006362

碩士 === 國立清華大學 === 資訊工程學系 === 94 === Placement always plays an important part in a back-end design flow and is an active research area for many years, because it significantly affects the routability, chip size, chip power, and chip performance. In this thesis, we propose a timing-aware standard-cell placement algorithm, which introduces a new force (timing force) into a force directed based placer to optimize wirelength and timing concurrently. We combine our method with a wirelength-driven placer, and want to find smaller wirelength with better circuit performance. Experimental results show that our method achieves average routed wirelength reduction by 1.8% and 7.8% as compared to an existing wirelength-driven placer and to a commercial placer, respectively. At the same time, the critical path delays of five test cases are also averagely reduced by 2.2% and 2.6%, respectively.