Test Controller for Delay Fault Testing Based on IEEE 1500 Architecture
碩士 === 國立清華大學 === 電機工程學系 === 94 === Abstract In order to reduce design time, the reusable IP cores become primary design trend. Issue about delay fault testing becomes more important because of the high performance requirement in VLSI chip. To achieve high performance, VLSI chips need to work corr...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82062447254979245185 |