A Priority Assignment Strategy of Processing Elements over an On-Chip Bus
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 94 === The number of bus transactions in multimedia SoC grows significantly in recent years. Because of different timing requirements for different applications, how to find a proper priority assignment for processing elements (PEs) of SoC becomes very challenging. In...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/61159618652418753863 |
| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 94 === The number of bus transactions in multimedia SoC grows significantly in recent years. Because of different timing requirements for different applications, how to find a proper priority assignment for processing elements (PEs) of SoC becomes very challenging. In this thesis, we first show that the priority assignment problem with one unique priority for each PE is NP-hard. When each bus transaction can have one unique priority, we propose an optimal priority assignment algorithm for a given bus transaction graph. We then propose a priority assignment strategy based on simulated annealing (SA) for PEs, where bus arbitration is done in a priority-driven fashion. The objective is to minimize the number of priorities needed for each PE and to satisfy the performance requirements of applications. The experimental results show some encouraging results in priority assignment.
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