| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === We are going to see the design process of a RISC processor for ARM
instructions. The processor is pipelined into 3 stages; fetch,
decode and execute. There are 44 input and 79 output pins, excluding
the power connections. The data and address bus are both 32-bit.
Highest frequency is 90MHz with 0.18 CMOS technology. The processor
supports virtual memory systems. Instruction set covers branch and
branch with link, data processing, program status register transfer,
multiply and multiply accumulate, single data transfer, block data
transfer, single data swap, software interrupt, coprocessor data
operations, coprocessor data transfers, coprocessor register
transfers and undefined instruction. We will start with building a
general idea about the architecture and IO signals of the processor.
Then we will see the instruction set of the processor including the
binary encoding of the instructions. We will examine the
organization of the components of the processor in third chapter.
Fourth chapter is about design flow ie, the transformation of the
design from an RTL code into a physical chip. In fifth chapter we
will se the simulation results of post-layout design. Then we will
end up with the conclusion.
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