A Delay Line Based Design-for-Test Technique for Sinusoidal Jitter Measurement
碩士 === 國立臺灣大學 === 電子工程學研究所 === 94 === In this thesis, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal’s cycle lengths without ext...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96074244147913428994 |